J-CPU - MOS 6510/8500 FPGA REPLACEMENT

J-PCU, FPGA 6510/8500

FPGA 6510/8500 - J-CPU

  • FPGA based replacement for MOS 6510 CPU
  • Project started in 2020 by designing PCB. No PCB was populated until summer 2022, when the project continued.
  • Project goal is to make 100% compatible FPGA replacement for MOS 6510, that is physically same size as original
  • One goal is to learn more about FPGA designing, so all the code is completely self written
  • October 2022 status:

  • About 80% complete. Already usable, with some issues with some games and demos
  • PCB needs some modifications
  • All standard instructions implemented
  • Cycle count not correct with all instructions
  • Decimal mode not implemented
  • Only some illegal instructions implemented so far
  • IRQ interrupts ok, NMI not implemented yet
  • RDY/AEC logic done and working. HALT timing needs to be checked
  • Bus timing needs to be checked and adjusted.
  • BACK / J-CIA / J-VIC / VIDS

    2020-2022 Jani Laatikainen